Vikas Chandra
Vikas Chandra
AI Research @ Facebook
Geverifieerd e-mailadres voor fb.com
Titel
Geciteerd door
Geciteerd door
Jaar
Throughput-optimized OpenCL-based FPGA accelerator for large-scale convolutional neural networks
N Suda, V Chandra, G Dasika, A Mohanty, Y Ma, S Vrudhula, J Seo, ...
Proceedings of the 2016 ACM/SIGDA International Symposium on Field …, 2016
3432016
Exploring sub-20nm FinFET design with predictive technology models
S Sinha, G Yeric, V Chandra, B Cline, Y Cao
DAC Design Automation Conference 2012, 283-288, 2012
2752012
FPGA switch block layout and evaluation
H Schmit, V Chandra
Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field …, 2002
1732002
Impact of technology and voltage scaling on the soft error susceptibility in nanoscale CMOS
V Chandra, R Aitken
2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI …, 2008
1592008
Bit fusion: Bit-level dynamically composable architecture for accelerating deep neural network
H Sharma, J Park, N Suda, L Lai, B Chau, V Chandra, H Esmaeilzadeh
2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture …, 2018
1112018
TIMBER: Time borrowing and error relaying for online timing error resilience
M Choudhury, V Chandra, K Mohanram, R Aitken
2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010 …, 2010
1062010
Federated learning with non-iid data
Y Zhao, M Li, L Lai, N Suda, D Civin, V Chandra
arXiv preprint arXiv:1806.00582, 2018
952018
Configurable IC with interconnect circuits that also perform storage operations
S Teig, H Schmit, J Redgrave, V Chandra
US Patent 7,342,415, 2008
942008
Hello edge: Keyword spotting on microcontrollers
Y Zhang, N Suda, L Lai, V Chandra
arXiv preprint arXiv:1711.07128, 2017
922017
Cmsis-nn: Efficient neural network kernels for arm cortex-m cpus
L Lai, N Suda, V Chandra
arXiv preprint arXiv:1801.06601, 2018
712018
On the efficacy of write-assist techniques in low voltage nanoscale SRAMs
V Chandra, C Pietrzyk, R Aitken
2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010 …, 2010
642010
Correlated electron switch programmable fabric
L Shifren, G Yeric, S Sinha, B Cline, V Chandra
US Patent 10,056,143, 2018
632018
Analytical model for TDDB-based performance degradation in combinational logic
M Choudhury, V Chandra, K Mohanram, R Aitken
2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010 …, 2010
612010
Device and technology implications of the Internet of Things
R Aitken, V Chandra, J Myers, B Sandhu, L Shifren, G Yeric
2014 Symposium on VLSI technology (VLSI-technology): digest of technical …, 2014
582014
Workload dependent NBTI and PBTI analysis for a sub-45nm commercial microprocessor
E Mintarno, V Chandra, D Pietromonaco, R Aitken, RW Dutton
2013 IEEE International Reliability Physics Symposium (IRPS), 3A. 1.1-3A. 1.6, 2013
522013
An interconnect channel design methodology for high performance integrated circuits
V Chandra, A Xu, H Schmit, L Pileggi
Proceedings Design, Automation and Test in Europe Conference and Exhibition …, 2004
492004
Slackprobe: A low overhead in situ on-line timing slack monitoring methodology
L Lai, V Chandra, R Aitken, P Gupta
2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), 282-287, 2013
482013
Comprehensive analysis of sequential and combinational soft errors in an embedded processor
M Ebrahimi, A Evans, MB Tahoori, E Costenaro, D Alexandrescu, ...
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2015
472015
Configurable IC with interconnect circuits that also perform storage operations
S Teig, H Schmit, J Redgrave, V Chandra
US Patent 7,545,167, 2009
472009
Impact of voltage scaling on nanoscale SRAM reliability
V Chandra, R Aitken
2009 Design, Automation & Test in Europe Conference & Exhibition, 387-392, 2009
472009
Het systeem kan de bewerking nu niet uitvoeren. Probeer het later opnieuw.
Artikelen 1–20