Danilo Šijačić
Danilo Šijačić
Ulvetanna Inc.
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Towards efficient and automated side channel evaluations at design time
D Šijačić, J Balasch, B Yang, S Ghosh, I Verbauwhede
Journal of Cryptographic Engineering (JCEN) 10, 305-319, 2020
A low-randomness second-order masked AES
T Beyne, S Dhooghe, A Ranea, D Šijačić
International Conference on Selected Areas in Cryptography, 87-110, 2021
Glitch-resistant masking schemes as countermeasure against fault sensitivity analysis
V Arribas, T De Cnudde, D Šijačić
2018 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC), 27-34, 2018
Sweeping for Leakage in Masked Circuit Layouts
D Sijacic, I Verbauwhede, J Balasch
2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2020
Hold your breath, PRIMATEs are lightweight
D Šijačić, AB Kidmose, B Yang, S Banik, B Bilgin, A Bogdanov, ...
Selected Areas in Cryptography–SAC 2016: 23rd International Conference, St …, 2017
Design Time Evaluation for Side-Channel Attack Resistant Cryptographic Implementations
D Šijačić
Generalized Matsui Algorithm 1 with application for the full DES
T Ashur, R Posteuca, D Šijačić, S D’haeseleer
Security and Cryptography for Networks: 12th International Conference, SCN …, 2020
Extreme Pipelining Towards the Best Area-Performance Trade-Off in Hardware
S Picek, D Sisejkovic, D Jakobovic, L Batina, B Yang, D Šijačić, ...
International Conference on Cryptology in Africa, 147-166, 2016
Vision Mark-32: ZK-Friendly Hash Function Over Binary Tower Fields
T Ashur, M Mahzoun, J Posen, D Šijačić
Cryptology ePrint Archive, 2024
Towards efficient and automated side-channel evaluations at design time
D Sijacic, J Balasch, B Yang, S Ghosh, I Verbauwhede
Journal of Cryptographic Engineering 10 (4), 305-319, 2020
The Strictly Zero-Correlation Attack with Application to the Full DES
T Ashur, R Posteuca, D Šijačić, S D'haeseleer
IACR Cryptol. ePrint Arch. 2020 (523), 15, 2020
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