Mohammad Khavari Tavana
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Two-State Checkpointing for Energy-Efficient Fault Tolerance in Hard Real-Time Systems
M Salehi, MK Tavana, S Rehman, M Shafique, A Ejlali, J Henkel
Transactions on Very Large Scale Integration (VLSI) Systems 24 (7), 2426 - 2437, 2016
DRVS: Power-efficient reliability management through dynamic redundancy and voltage scaling under variations
M Salehi, MK Tavana, S Rehman, F Kriebel, M Shafique, A Ejlali, ...
2015 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2015
Energy-efficient mapping of biomedical applications on domain-specific accelerator under process variation
MK Tavana, A Kulkarni, A Rahimi, T Mohsenin, H Homayoun
2014 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2014
Feedback-based energy management in a standby-sparing scheme for hard real-time systems
MK Tavana, M Salehi, A Ejlali
2011 IEEE 32nd Real-Time Systems Symposium, 349-356, 2011
Wide I/O or LPDDR? Exploration and analysis of performance, power and temperature trade-offs of emerging DRAM technologies in embedded MPSoCs
MH Hajkazemi, MK Tavana, H Homayoun
2015 33rd IEEE International Conference on Computer Design (ICCD), 62-69, 2015
ElasticCore: enabling dynamic heterogeneity with joint core and voltage/frequency scaling
MK Tavana, MH Hajkazemi, D Pathak, I Savidis, H Homayoun
Proceedings of the 52nd Annual Design Automation Conference, 1-6, 2015
dsReliM: Power-constrained reliability management in dark-silicon many-core chips under process variations
M Salehi, M Shafique, F Kriebel, S Rehman, MK Tavana, A Ejlali, ...
2015 International Conference on Hardware/Software Codesign and System …, 2015
Enabling dynamic heterogeneity through core-on-core stacking
V Kontorinis, MK Tavana, MH Hajkazemi, DM Tullsen, H Homayoun
Proceedings of the 51st Annual Design Automation Conference, 1-6, 2014
Exploring the potential for collaborative data compression and hard-error tolerance in pcm memories
A Jadidi, M Arjomand, MK Tavana, DR Kaeli, MT Kandemir, CR Das
2017 47th Annual IEEE/IFIP International Conference on Dependable Systems …, 2017
Realizing complexity-effective on-chip power delivery for many-core platforms by exploiting optimized mapping
MK Tavana, D Pathak, MH Hajkazemi, M Malik, I Savidis, H Homayoun
2015 33rd IEEE International Conference on Computer Design (ICCD), 581-588, 2015
REMAP: A reliability/endurance mechanism for advancing PCM
MK Tavana, AK Ziabari, M Arjomand, M Kandemir, C Das, D Kaeli
Proceedings of the International Symposium on Memory Systems, 385-398, 2017
Live together or die alone: Block cooperation to extend lifetime of resistive memories
MK Tavana, AK Ziabari, D Kaeli
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017
Exploiting Adaptive Data Compression to Improve Performance and Energy-efficiency of Compute Workloads in Multi-GPU Systems
MK Tavana, Y Sun, NB Agostini, D Kaeli
33rd International Parallel and Distributed Processing Symposium, 2019
Cost-effective write disturbance mitigation techniques for advancing PCM density
MK Tavana, D Kaeli
2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 253-260, 2017
Energy efficient on-chip power delivery with run-time voltage regulator clustering
D Pathak, MH Hajkazemi, MK Tavana, H Homayoun, I Savidis
2016 IEEE International Symposium on Circuits and Systems (ISCAS), 1210-1213, 2016
Adaptive bandwidth management for performance-temperature trade-offs in heterogeneous HMC+ DDRx memory
MH Hajkazemi, M Chorney, R Jabbarvand Behrouz, M Khavari Tavana, ...
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, 391-396, 2015
Dynamically adaptive register file architecture for energy reduction in embedded processors
MK Tavana, SA Khameneh, M Goudarzi
Microprocessors and Microsystems 39 (2), 49-63, 2015
ONC3: All-optical NoC based on cube-connected cycles with quasi-DOR algorithm
M Abdollahi, MK Tavana, S Koohi, S Hessabi
2012 15th Euromicro Conference on Digital System Design, 296-303, 2012
Nacre** Nacre, or mother-of-pearl, is one of nature's remarkable examples of a durable and break-resistant structure.: Durable, Secure and Energy-Efficient Non-Volatile Memory …
MK Tavana, Y Fei, D Kaeli
IEEE Annals of the History of Computing 8 (04), 897-906, 2020
Heterogeneous HMC+ DDRx memory management for performance-temperature tradeoffs
MH Hajkazemi, MK Tavana, T Mohsenin, H Homayoun
ACM Journal on Emerging Technologies in Computing Systems (JETC) 14 (1), 1-21, 2017
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