| Design issues and considerations for low-cost 3-D TSV IC technology G Van der Plas, P Limaye, I Loi, A Mercha, H Oprins, C Torregiani, S Thijs, ... IEEE Journal of Solid-State Circuits 46 (1), 293-307, 2010 | 342 | 2010 |
| Network-on-chip design and synthesis outlook D Atienza, F Angiolini, S Murali, A Pullini, L Benini, G De Micheli Integration 41 (3), 340-359, 2008 | 161 | 2008 |
| Fault tolerance overhead in network-on-chip flow control schemes A Pullini, F Angiolini, D Bertozzi, L Benini 2005 18th Symposium on Integrated Circuits and Systems Design, 224-229, 2005 | 121 | 2005 |
| Near-threshold RISC-V core with DSP extensions for scalable IoT endpoint devices M Gautschi, PD Schiavone, A Traber, I Loi, A Pullini, D Rossi, E Flamand, ... IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (10 …, 2017 | 105 | 2017 |
| Bringing NoCs to 65 nm A Pullini, F Angiolini, S Murali, D Atienza, G De Micheli, L Benini IEEE Micro 27 (5), 75-85, 2007 | 96 | 2007 |
| An IoT endpoint system-on-chip for secure and energy-efficient near-sensor analytics F Conti, R Schilling, PD Schiavone, A Pullini, D Rossi, FK Gürkaynak, ... IEEE Transactions on Circuits and Systems I: Regular Papers 64 (9), 2481-2494, 2017 | 75 | 2017 |
| NoC design and implementation in 65nm technology A Pullini, F Angiolini, P Meloni, D Atienza, S Murali, L Raffo, G De Micheli, ... First International Symposium on Networks-on-Chip (NOCS'07), 273-282, 2007 | 75 | 2007 |
| Networks on chips: From research to products G De Micheli, C Seiculescu, S Murali, L Benini, F Angiolini, A Pullini Proceedings of the 47th Design Automation Conference, 300-305, 2010 | 59 | 2010 |
| A 60 gops/w,− 1.8 v to 0.9 v body bias ulp cluster in 28 nm utbb fd-soi technology D Rossi, A Pullini, I Loi, M Gautschi, FK Gürkaynak, A Bartolini, ... Solid-State Electronics 117, 170-184, 2016 | 53 | 2016 |
| PULP: A ultra-low power parallel accelerator for energy-efficient and flexible embedded vision F Conti, D Rossi, A Pullini, I Loi, L Benini Journal of Signal Processing Systems 84 (3), 339-354, 2016 | 50 | 2016 |
| PULP: A parallel ultra low power platform for next generation IoT applications D Rossi, F Conti, A Marongiu, A Pullini, I Loi, M Gautschi, G Tagliavini, ... 2015 IEEE Hot Chips 27 Symposium (HCS), 1-39, 2015 | 41 | 2015 |
| Design of compact imperfection-immune CNFET layouts for standard-cell-based logic synthesis S Bobba, J Zhang, A Pullini, D Atienza, G De Micheli 2009 Design, Automation & Test in Europe Conference & Exhibition, 616-621, 2009 | 41 | 2009 |
| PULPino: A small single-core RISC-V SoC A Traber, F Zaruba, S Stucki, A Pullini, G Haugou, E Flamand, ... 3rd RISCV Workshop, 2016 | 36 | 2016 |
| Timing-driven row-based power gating A Sathanur, A Pullini, L Benini, A Macii, E Macii, M Poncino Proceedings of the 2007 international symposium on Low power electronics and …, 2007 | 36 | 2007 |
| 193 MOPS/mW@ 162 MOPS, 0.32 V to 1.15 V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing D Rossi, A Pullini, I Loi, M Gautschi, FK Gurkaynak, A Teman, ... 2016 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS XIX), 1-3, 2016 | 35 | 2016 |
| Slow and steady wins the race? a comparison of ultra-low-power risc-v cores for internet-of-things applications PD Schiavone, F Conti, D Rossi, M Gautschi, A Pullini, E Flamand, ... 2017 27th International Symposium on Power and Timing Modeling, Optimization …, 2017 | 32 | 2017 |
| Energy-efficient near-threshold parallel computing: The pulpv2 cluster D Rossi, A Pullini, I Loi, M Gautschi, FK Gürkaynak, A Teman, ... Ieee Micro 37 (5), 20-31, 2017 | 29 | 2017 |
| Energy-efficient vision on the PULP platform for ultra-low power parallel computing F Conti, D Rossi, A Pullini, I Loi, L Benini 2014 IEEE Workshop on Signal Processing Systems (SiPS), 1-6, 2014 | 29 | 2014 |
| Tailoring instruction-set extensions for an ultra-low power tightly-coupled cluster of OpenRISC cores M Gautschi, A Traber, A Pullini, L Benini, M Scandale, A Di Federico, ... 2015 IFIP/IEEE International Conference on Very Large Scale Integration …, 2015 | 28 | 2015 |
| Timing-error-tolerant network-on-chip design methodology R Tamhankar, S Murali, S Stergiou, A Pullini, F Angiolini, L Benini, ... IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2007 | 28 | 2007 |
Luca BeniniETH Zürich, Università di BolognaVerified email at unibo.it
