Flavio M de Paula
Flavio M de Paula
IBM Corporation
Verified email at cs.ubc.ca - Homepage
Title
Cited by
Cited by
Year
Backspace: Formal analysis for post-silicon debug
FM De Paula, M Gort, AJ Hu, SJE Wilton, J Yang
2008 Formal Methods in Computer-Aided Design, 1-10, 2008
892008
Industrial strength distributed explicit state model checking
B Bingham, J Bingham, FM De Paula, J Erickson, G Singh, M Reitblatt
2010 Ninth International Workshop on Parallel and Distributed Methods in …, 2010
532010
An effective guidance strategy for abstraction-guided simulation
FM De Paula, AJ Hu
2007 44th ACM/IEEE Design Automation Conference, 63-68, 2007
472007
TAB-BackSpace: Unlimited-length trace buffers with zero additional on-chip overhead
FM de Paula, A Nahir, Z Nevo, A Orni, AJ Hu
Proceedings of the 48th Design Automation Conference, 411-416, 2011
232011
The Chip is Ready. Am I done? On-chip Verification using Assertion Processors.
JAM Nacif, FM de Paula, H Foster, CJN Coelho Jr, AO Fernandes
VLSI-SOC, 111-, 2003
222003
An assertion library for on-chip white-box verification at run-time
JA Nacif, FM de Paula, H Foster, C Coelho, FC Sica, DC da Silva, ...
Proceedings of Latin American Test WorkShop, 2003
172003
nuTAB-BackSpace: Rewriting to normalize non-determinism in post-silicon debug traces
FM De Paula, AJ Hu, A Nahir
International Conference on Computer Aided Verification, 513-531, 2012
132012
Formal-analysis-based trace computation for post-silicon debug
M Gort, FM De Paula, JJW Kuan, TM Aamodt, AJ Hu, SJE Wilton, J Yang
IEEE transactions on very large scale integration (VLSI) systems 20 (11 …, 2011
112011
Lazy suspect-set computation: Fault diagnosis for deep electrical bugs
D Sengupta, FM De Paula, AJ Hu, A Veneris, A Ivanov
Proceedings of the great lakes symposium on VLSI, 189-194, 2012
52012
BackSpace: Moving towards reality
FM De Paula, M Gort, AJ Hu, SJE Wilton
2008 Ninth International Workshop on Microprocessor Test and Verification, 49-54, 2008
42008
EverLost: A flexible platform for industrial-strength abstraction-guided simulation
FM de Paula, AJ Hu
International Conference on Computer Aided Verification, 282-285, 2006
32006
Application level hardware tracing for scaling post-silicon debug
D Pal, A Sharma, S Ray, FM De Paula, S Vasudevan
Proceedings of the 55th Annual Design Automation Conference, 1-6, 2018
22018
An efficient rewriting framework for trace coverage of symmetric systems
FM De Paula, A Haran, B Bingham
NASA Formal Methods Symposium, 95-112, 2018
12018
PREACH: A distributed explicit state model checker
FM De Paula, B Bingham, J Bingham, J Erickson, M Reitblatt, G Singh
Technical Report TR-2010-05, University of British Columbia, 2010
12010
Refactoring digital hardware designs with assertion libraries
FM De Paula, CN Coelho, H Foster, JA Nacif, J Tompkins, AO Fernandes, ...
Eighth IEEE International High-Level Design Validation and Test Workshop, 37-42, 2003
12003
TRACE-BASED GENERATION OF STATES WITHIN A SYSTEM
FM De Paula, BD Bingham, A Haran
US Patent App. 16/295,734, 2020
2020
Rewriting toward trace coverage analysis of symmetric systems
FM De Paula, A Haran, B Bingham
Innovations in Systems and Software Engineering 15 (3-4), 191-206, 2019
2019
On-Chip Property Verification Using Assertion Processors
JAM Nacif, CN Coelho, H Foster, FM de Paula, E Mota, MRF Mota, ...
VLSI-SOC: From Systems to Chips, 101-117, 2006
2006
The DATE Executive Committee gratefully acknowledges the assistance of the following persons in the review process.
S Abdi, G Agosta, J Ahmed, Y Ahn, B Akesson, N Alves, F Amiel, K Amiri, ...
BackSpace: Form al Analysis for Post-Silicon D ebug
AJ Hu
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