| A programmable method for low-power scan shift in SoC integrated circuits R Wang, B Bhaskaran, K Natarajan, A Abdollahian, K Narayanun, ... 2016 IEEE 34th VLSI Test Symposium (VTS), 1-6, 2016 | 24 | 2016 |
| DFT techniques and automation for asynchronous NULL conventional logic circuits V Satagopan, B Bhaskaran, WK Al-Assadi, SC Smith, S Kakarla IEEE transactions on very large scale integration (VLSI) systems 15 (10 …, 2007 | 20 | 2007 |
| Special session: in-system-test (ist) architecture for nvidia drive-agx platforms PKD Jagannadha, M Yilmaz, M Sonawane, S Chadalavada, S Sarangi, ... 2019 IEEE 37th VLSI Test Symposium (VTS), 1-8, 2019 | 17 | 2019 |
| Advanced test methodology for complex SoCs PKD Jagannadha, M Yilmaz, M Sonawane, S Chadalavada, S Sarangi, ... 2016 IEEE International Test Conference (ITC), 1-10, 2016 | 15 | 2016 |
| An efficient supervised learning method to predict power supply noise during at-speed test SN Mozaffari, B Bhaskaran, K Narayanun, A Abdollahian, V Pagalone, ... 2019 IEEE International Test Conference (ITC), 1-10, 2019 | 10 | 2019 |
| A novel graph coloring based solution for low-power scan shift S Gupta, B Bhaskaran, S Sarangi, A Abdollahian, J Dworak 2019 IEEE 37th VLSI Test Symposium (VTS), 1-6, 2019 | 8 | 2019 |
| Automated energy calculation and estimation for delay-insensitive digital circuits V Satagopan, B Bhaskaran, A Singh, SC Smith Microelectronics journal 38 (10-11), 1095-1107, 2007 | 7 | 2007 |
| Implementation of Design For Test for Asynchronous NCL Designs. B Bhaskaran, V Satagopan, WK Al-Assadi, SC Smith CDES, 78-84, 2005 | 7 | 2005 |
| Test method and scheme for low-power validation in modern SoC integrated circuits B Bhaskaran, A Sanghani, K Narayanun, A Abdollahian, A Laknaur 2016 IEEE 34th VLSI Test Symposium (VTS), 1-6, 2016 | 6 | 2016 |
| Automated synthesis and cycle reduction optimization for asynchronous NULL convention circuits using industry-standard CAD tools B Bhaskaran PhD thesis, University of Missouri–Rolla, Rolla, MO, 2007 | 5 | 2007 |
| Automation in design for test for asynchronous null conventional logic (NCL) circuits V Satagopan, B Bhaskaran, W Al-Assadi, SC Smith 12th NASA Symp. VLSI Des., Coeur d’Alene, ID, 2005 | 4 | 2005 |
| At-speed capture global noise reduction & low-power memory test architecture B Bhaskaran, S Chadalavada, S Sarangi, N Valentine, VAR Nerallapally, ... 2017 IEEE 35th VLSI Test Symposium (VTS), 1-6, 2017 | 3 | 2017 |
| Performing testing utilizing staggered clocks S Chadalavada, VAR Nerallapally, JD Kurien, B Bhaskaran, M Sonawane, ... US Patent 11,668,750, 2023 | 1 | 2023 |
| Observation Point Insertion Using Deep Learning B Bhaskaran, S Banerjee, K Narayanun, SC Hung, SNM Mojaveri, M Liu, ... Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided …, 2022 | 1 | 2022 |
| High-Speed Energy Estimation for Delay-Insensitive Circuits. B Bhaskaran, V Satagopan, SC Smith CDES, 35-41, 2005 | 1 | 2005 |
| Technique for enabling on-die noise measurement during ate testing and ist B Bhaskaran, N Valentine, S Sarangi, M Yilmaz, S Satheesh, C Hwang, ... US Patent App. 17/979,246, 2023 | | 2023 |
| On-Die Noise Measurement During Automatic Test Equipment (ATE) Testing and In-System-Test (IST) SN Mozaffari, B Bhaskaran, S Sarangi, S Satheesh, KL Fu, N Valentine, ... 2022 IEEE 40th VLSI Test Symposium (VTS), 1-6, 2022 | | 2022 |
| Field adaptable in-system test mechanisms S Chadalavada, SK Sarangi, MB Sonawane, S Bhavsar, J Wu, ... US Patent 10,746,798, 2020 | | 2020 |
| Automated synthesis and NULL cycle reduction optimization for asynchronous NULL convention circuits using industry-standard CAD tools B Bhaskaran University of Missouri--Rolla, 2007 | | 2007 |
| Design for Test Techniques for Asynchronous NULL Conventional Logic (NCL) Circuits V Satagopan, B Bhaskaran, WK Al-Assadi, SC Smith, S Kakarla Advances and Innovations in Systems, Computing Sciences and Software …, 2007 | | 2007 |
