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Nicolò Pinna
Nicolò Pinna
Process Integrator, ASML
Geverifieerd e-mailadres voor asml.com - Homepage
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Record 47 mV/dec top-down vertical nanowire InGaAs/GaAsSb tunnel FETs
A Alian, S El Kazzi, A Verhulst, A Milenin, N Pinna, T Ivanov, D Lin, ...
2018 IEEE Symposium on VLSI Technology, 133-134, 2018
222018
Alternative metals: from ab initio screening to calibrated narrow line models
C Adelmann, K Sankaran, S Dutta, A Gupta, S Kundu, G Jamieson, ...
2018 IEEE International Interconnect Technology Conference (IITC), 154-156, 2018
202018
Record performance Top-down In0.53Ga0.47As vertical nanowire FETs and vertical nanosheets
S Ramesh, T Ivanov, V Putcha, A Alian, A Sibaja-Hernandez, ...
2017 IEEE International Electron Devices Meeting (IEDM), 17.1. 1-17.1. 4, 2017
202017
IEEE International Interconnect Technology Conference (IITC)
C Adelmann, K Sankaran, S Dutta, A Gupta, S Kundu, G Jamieson, ...
IEEE, 2018
122018
Understanding the factors affecting contact resistance in nanowire field effect transistors (NWFETs) to improve nanoscale contacts for future scaling
S Ramesh, T Ivanov, A Sibaja-Hernandez, A Alian, E Camerotto, ...
Journal of Applied Physics 132 (2), 2022
32022
Tuning of electrical properties in few layer CVD MoS2 through reduction of ambient exposure
A Leonhardt, D Chiappe, I Asselberghs, N Pinna, A Dabral, A Nalin Mehta, ...
E-MRS Fall Meeting, Date: 2017/01/01-2017/01/09, Location: Warsaw Poland, 2017
2017
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Artikelen 1–6