| A hardware scheduler for real time multiprocessor system on chip N Gupta, SK Mandal, J Malave, A Mandal, RN Mahapatra 2010 23rd International Conference on VLSI Design, 264-269, 2010 | 36 | 2010 |
| NoCBench: a benchmarking platform for network on chip SK Mandal, N Gupta, A Mandal, J Malave, JD Lee, R Mahapatra Workshop on Unique Chips and Systems (UCAS), 2009 | 30 | 2009 |
| A fast, source-synchronous ring-based network-on-chip design A Mandal, SP Khatri, RN Mahapatra 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2012 | 13 | 2012 |
| Interconnected tile standing wave resonant oscillator based clock distribution circuits A Mandal, V Karkala, SP Khatri, RN Mahapatra 2011 24th Internatioal Conference on VLSI Design, 82-87, 2011 | 12 | 2011 |
| An efficient arithmetic sum-of-product (SOP) based multiplication approach for FIR filters and DFT R Kumar, A Mandal, SP Khatri 2012 IEEE 30th International Conference on Computer Design (ICCD), 195-200, 2012 | 7 | 2012 |
| A low-jitter phase-locked resonant clock generation and distribution scheme A Mandal, KC Bollapalli, N Jayakumar, SP Khatri, RN Mahaptra 2013 IEEE 31st International Conference on Computer Design (ICCD), 487-490, 2013 | 6 | 2013 |
| A bio-inspired framework for secure system on chip A Mandal, S Mandal, A Tripathy, N Gupta, R Mahapatra 1st Workshop on SoC Architecture, Accelerators and Workloads, 2010 | 6 | 2010 |
| Boolean satisfiability using noise based logic PCK Lin, A Mandal, SP Khatri Proceedings of the 49th Annual Design Automation Conference, 1260-1261, 2012 | 5 | 2012 |
| Exploring topologies for source-synchronous ring-based network-on-chip A Mandal, SP Khatri, RN Mahapatra 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2013 | 4 | 2013 |
| Architectural simulations of a fast, source-synchronous ring-based Network-on-Chip design A Mandal, SP Khatri, RN Mahapatra 2012 IEEE 30th International Conference on Computer Design (ICCD), 482-483, 2012 | 3 | 2012 |
| An automated approach for minimum jitter buffered h-tree construction A Mandal, N Jayakumar, K Bollapalli, SP Khatri, RN Mahapatra 2011 24th Internatioal Conference on VLSI Design, 76-81, 2011 | 3 | 2011 |
| Source-Synchronous Networks-On-Chip: Circuit and Architectural Interconnect Modeling A Mandal, SP Khatri, R Mahapatra Springer Science & Business Media, 2013 | 2 | 2013 |
| A Source-synchronous Htree-based Network-on-chip A Mandal, SP Khatri, RN Mahapatra Proceedings of the 23rd ACM international conference on Great lakes …, 2013 | 2 | 2013 |
| Efficient design and clocking for a network-on-chip A Mandal Texas A&M University, 2013 | 2 | 2013 |
| Fast Network-on-Chip Design A Mandal, SP Khatri, R Mahapatra, A Mandal, SP Khatri, RN Mahapatra Source-Synchronous Networks-On-Chip: Circuit and Architectural Interconnect …, 2014 | | 2014 |
| Clock Distribution for Fast Networks-on-Chip A Mandal, SP Khatri, R Mahapatra, A Mandal, SP Khatri, RN Mahapatra Source-Synchronous Networks-On-Chip: Circuit and Architectural Interconnect …, 2014 | | 2014 |
| Fast On-Chip Data Transfer Using Sinusoid Signals A Mandal, SP Khatri, R Mahapatra, A Mandal, SP Khatri, RN Mahapatra Source-Synchronous Networks-On-Chip: Circuit and Architectural Interconnect …, 2014 | | 2014 |
| Alleviating NBTI-induced failure in off-chip output drivers B Bhadviya, A Mandal, SP Khatri Proceedings of the great lakes symposium on VLSI, 295-298, 2012 | | 2012 |
