| Reactant minimization during sample preparation on digital microfluidic biochips using skewed mixing trees JD Huang, CH Liu, TW Chiang Proceedings of the International Conference on Computer-Aided Design, 377-383, 2012 | 103 | 2012 |
| Reactant and waste minimization in multitarget sample preparation on digital microfluidic biochips JD Huang, CH Liu, HS Lin IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2013 | 54 | 2013 |
| Graph-based optimal reactant minimization for sample preparation on digital microfluidic biochips TW Chiang, CH Liu, JD Huang 2013 International Symposium onVLSI Design, Automation, and Test (VLSI-DAT), 1-4, 2013 | 51 | 2013 |
| Dilution and mixing algorithms for flow-based microfluidic biochips S Bhattacharjee, S Poddar, S Roy, JD Huang, BB Bhattacharya IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2016 | 50 | 2016 |
| Sample preparation for many-reactant bioassay on DMFBs using common dilution operation sharing CH Liu, HH Chang, TC Liang, JD Huang 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 615-621, 2013 | 45 | 2013 |
| Lambda set selection in Roth-Karp decomposition for LUT-based FPGA technology mapping WZ Shen, JD Huang, SM Chao Proceedings of the 32nd annual ACM/IEEE Design Automation Conference, 65-69, 1995 | 45 | 1995 |
| ALTO: An iterative area/performance tradeoff algorithm for LUT-based FPGA technology mapping JD Huang, JY Jou, WZ Shen IEEE transactions on very large scale integration (VLSI) systems 8 (4), 392-400, 2000 | 43 | 2000 |
| Equivalence checking of scheduling with speculative code transformations in high-level synthesis CH Lee, CH Shih, JD Huang, JY Jou 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011), 497-502, 2011 | 40 | 2011 |
| A precise bandwidth control arbitration algorithm for hard real-time SoC buses BC Lin, GW Lee, JD Huang, JY Jou 2007 Asia and South Pacific Design Automation Conference, 165-170, 2007 | 34 | 2007 |
| Compatible class encoding in Roth-Karp decomposition for two-output LUT architecture JD Huang, JY Jou, WZ Shen Proceedings of IEEE International Conference on Computer Aided Design (ICCAD …, 1995 | 34 | 1995 |
| A real-time and bandwidth guaranteed arbitration algorithm for SoC bus communication CH Chen, GW Lee, JD Huang, JY Jou Proceedings of the 2006 Asia and South Pacific Design Automation Conference …, 2006 | 31 | 2006 |
| Reactant minimization in sample preparation on digital microfluidic biochips CH Liu, TW Chiang, JD Huang IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2015 | 30 | 2015 |
| Compatible class encoding in hyper-function decomposition for FPGA synthesis JHR Jiang, JY Jou, JD Huang Proceedings of the 35th annual Design Automation Conference, 712-717, 1998 | 29 | 1998 |
| Volume-oriented sample preparation for reactant minimization on flow-based microfluidic biochips with multi-segment mixers CM Huang, CH Liu, JD Huang 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2015 | 22 | 2015 |
| Fine-grained bandwidth control arbiter and the method thereof JD Huang, BC Lin, GW Lee, JY Jou US Patent 7,577,780, 2009 | 21 | 2009 |
| Layer-aware design partitioning for vertical interconnect minimization YS Huang, YH Liu, JD Huang 2011 IEEE Computer Society Annual Symposium on VLSI, 144-149, 2011 | 20 | 2011 |
| Input selection encoding for low power multiplexer tree HE Chang, JD Huang, CI Chen 2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 1-4, 2007 | 19 | 2007 |
| Low power multiplexer tree design using dynamic propagation path control NS Li, JD Huang, HJ Huang APCCAS 2008-2008 IEEE Asia Pacific Conference on Circuits and Systems, 838-841, 2008 | 17 | 2008 |
| A comprehensive security system for digital microfluidic biochips CY Lin, JD Huang, H Yao, TY Ho 2018 IEEE International Test Conference in Asia (ITC-Asia), 151-156, 2018 | 16 | 2018 |
| Reactant minimization for sample preparation on microfluidic biochips with various mixing models CH Liu, KC Shen, JD Huang IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2015 | 16 | 2015 |
