Dr. Jonathan Woodruff
Dr. Jonathan Woodruff
Research Associate, Cambridge University
Geverifieerd e-mailadres voor cam.ac.uk
Titel
Geciteerd door
Geciteerd door
Jaar
The CHERI capability model: Revisiting RISC in an age of risk
J Woodruff, RNM Watson, D Chisnall, SW Moore, J Anderson, B Davis, ...
2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA …, 2014
2182014
Cheri: A hybrid capability-system architecture for scalable software compartmentalization
RNM Watson, J Woodruff, PG Neumann, SW Moore, J Anderson, ...
2015 IEEE Symposium on Security and Privacy, 20-37, 2015
1742015
Beyond the PDP-11: Architectural support for a memory-safe C abstract machine
D Chisnall, C Rothwell, RNM Watson, J Woodruff, M Vadera, SW Moore, ...
ACM SIGARCH Computer Architecture News 43 (1), 117-130, 2015
862015
Capability hardware enhanced risc instructions: Cheri instruction-set architecture (version 5)
RNM Watson, PG Neumann, J Woodruff, M Roe, J Anderson, D Chisnall, ...
University of Cambridge, Computer Laboratory, 2016
432016
Efficient tagged memory
A Joannou, J Woodruff, R Kovacsics, SW Moore, A Bradbury, H Xia, ...
2017 IEEE International Conference on Computer Design (ICCD), 641-648, 2017
362017
Fast protection-domain crossing in the CHERI capability-system architecture
RNM Watson, RM Norton, J Woodruff, SW Moore, PG Neumann, ...
IEEE Micro 36 (5), 38-49, 2016
322016
CHERI: a research platform deconflating hardware virtualisation and protection
RNM Watson, PG Neumann, J Woodruff, J Anderson, R Anderson, ...
Runtime Environments, Systems, Layering and Virtualized Environments (RESoLVE), 2012
302012
CheriABI: Enforcing valid pointer provenance and minimizing pointer privilege in the POSIX C run-time environment
B Davis, RNM Watson, A Richardson, PG Neumann, SW Moore, ...
Proceedings of the Twenty-Fourth International Conference on Architectural …, 2019
242019
CHERI JNI: Sinking the Java security model into the C
D Chisnall, B Davis, K Gudka, D Brazdil, A Joannou, J Woodruff, ...
ACM SIGARCH Computer Architecture News 45 (1), 569-583, 2017
242017
Capability hardware enhanced RISC instructions: CHERI instruction-set architecture
RNM Watson, PG Neumann, J Woodruff, M Roe, J Anderson, D Chisnall, ...
University of Cambridge, Computer Laboratory, 2015
212015
Cheri concentrate: Practical compressed capabilities
J Woodruff, A Joannou, H Xia, A Fox, RM Norton, D Chisnall, B Davis, ...
IEEE Transactions on Computers 68 (10), 1455-1469, 2019
202019
Capability hardware enhanced RISC instructions (CHERI): Notes on the Meltdown and Spectre attacks
RNM Watson, J Woodruff, M Roe, SW Moore, PG Neumann
University of Cambridge, Computer Laboratory, 2018
162018
CHERI: A RISC capability machine for practical memory safety
JD Woodruff
University of Cambridge, Computer Laboratory, 2014
162014
Cherivoke: Characterising pointer revocation using cheri capabilities for temporal memory safety
H Xia, J Woodruff, S Ainsworth, NW Filardo, M Roe, A Richardson, ...
Proceedings of the 52nd Annual IEEE/ACM International Symposium on …, 2019
142019
The CHERI capability model: Revisiting RISC in an age of risk. In 2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA)
J Woodruff, RNM Watson, D Chisnall, SW Moore, J Anderson, B Davis, ...
IEEE, 2014
142014
Bluespec Extensible RISC Implementation: BERI Hardware reference
RNM Watson, J Woodruff, D Chisnall, B Davis, W Koszek, AT Markettos, ...
University of Cambridge, Computer Laboratory, 2015
132015
Capability Hardware Enhanced RISC Instructions: CHERI Programmer’s Guide
RNM Watson, D Chisnall, B Davis, W Koszek, SW Moore, SJ Murdoch, ...
University of Cambridge, Computer Laboratory, 2015
112015
Cornucopia: Temporal Safety for CHERI Heaps
NW Filardo, BF Gutstein, J Woodruff, S Ainsworth, L Paul-Trifu, B Davis, ...
2020 IEEE Symposium on Security and Privacy (SP), 608-625, 2020
92020
CheriRTOS: A Capability Model for Embedded Devices
H Xia, J Woodruff, H Barral, L Esswood, A Joannou, R Kovacsics, ...
2018 IEEE 36th International Conference on Computer Design (ICCD), 92-99, 2018
62018
Capability Hardware Enhanced RISC Instructions: CHERI User’s guide
RNM Watson, D Chisnall, B Davis, W Koszek, SW Moore, SJ Murdoch, ...
University of Cambridge, Computer Laboratory, 2014
42014
Het systeem kan de bewerking nu niet uitvoeren. Probeer het later opnieuw.
Artikelen 1–20