Swarup Bhunia
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Hardware Trojan attacks: Threat analysis and countermeasures
S Bhunia, MS Hsiao, M Banga, S Narasimhan
Proceedings of the IEEE 102 (8), 1229-1247, 2014
4122014
Hardware Trojan: Threats and emerging solutions
RS Chakraborty, S Narasimhan, S Bhunia
2009 IEEE International high level design validation and test workshop, 166-171, 2009
3712009
MERO: A Statistical Approach for Hardware Trojan Detection
RS Chakraborty, F Wolff, S Paul, C Papachristou, S Bhunia
International Workshop on Cryptographic Hardware and Embedded Systems, 396-410, 2009
3612009
HARPOON: an obfuscation-based SoC design methodology for hardware protection
RS Chakraborty, S Bhunia
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2009
3502009
Towards Trojan-free trusted ICs: Problem analysis and detection scheme
F Wolff, C Papachristou, S Bhunia, RS Chakraborty
2008 Design, Automation and Test in Europe, 1362-1365, 2008
3502008
Electromechanical computing at 500 C with silicon carbide
TH Lee, S Bhunia, M Mehregany
Science 329 (5997), 1316-1318, 2010
1952010
Hardware trojans: Lessons learned after one decade of research
K Xiao, D Forte, Y Jin, R Karri, S Bhunia, M Tehranipoor
ACM Transactions on Design Automation of Electronic Systems (TODAES) 22 (1 …, 2016
1902016
Security against hardware Trojan through a novel application of design obfuscation
RS Chakraborty, S Bhunia
2009 IEEE/ACM International Conference on Computer-Aided Design-Digest of …, 2009
1812009
Hardware Trojan detection by multiple-parameter side-channel analysis
S Narasimhan, D Du, RS Chakraborty, S Paul, FG Wolff, CA Papachristou, ...
IEEE Transactions on computers 62 (11), 2183-2195, 2012
1652012
Low-power scan design using first-level supply gating
S Bhunia, H Mahmoodi, D Ghosh, S Mukhopadhyay, K Roy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 13 (3), 384-395, 2005
1562005
Deterministic clock gating for microprocessor power reduction
H Li, S Bhunia, Y Chen, TN Vijaykumar, K Roy
The Ninth International Symposium on High-Performance Computer Architecture …, 2003
1382003
Multiple-parameter side-channel analysis: A non-invasive hardware Trojan detection approach
S Narasimhan, D Du, RS Chakraborty, S Paul, F Wolff, C Papachristou, ...
2010 IEEE international symposium on hardware-oriented security and trust …, 2010
1372010
Hardware protection and authentication through netlist level obfuscation
RS Chakraborty, S Bhunia
2008 IEEE/ACM International Conference on Computer-Aided Design, 674-677, 2008
1332008
Protection against hardware trojan attacks: Towards a comprehensive solution
S Bhunia, M Abramovici, D Agrawal, P Bradley, MS Hsiao, J Plusquellic, ...
IEEE Design & Test 30 (3), 6-17, 2013
1212013
On-demand transparency for improving hardware Trojan detectability
RS Chakraborty, S Paul, S Bhunia
2008 IEEE International Workshop on Hardware-Oriented Security and Trust, 48-50, 2008
1192008
CRISTA: A new paradigm for low-power, variation-tolerant, and adaptive circuit synthesis using critical path isolation
S Ghosh, S Bhunia, K Roy
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2007
1192007
Self-referencing: A scalable side-channel approach for hardware Trojan detection
D Du, S Narasimhan, RS Chakraborty, S Bhunia
International Workshop on Cryptographic Hardware and Embedded Systems, 173-187, 2010
1082010
TeSR: A robust temporal self-referencing approach for hardware Trojan detection
S Narasimhan, X Wang, D Du, RS Chakraborty, S Bhunia
2011 IEEE International Symposium on Hardware-Oriented Security and Trust, 71-74, 2011
1062011
Vim-scan: A low overhead scan design approach for protection of secret key in scan-based secure chips
S Paul, RS Chakraborty, S Bhunia
25th IEEE VLSI Test Symposium (VTS'07), 455-460, 2007
1002007
Process variations and process-tolerant design
S Bhunia, S Mukhopadhyay, K Roy
20th international conference on VLSI design held jointly with 6th …, 2007
982007
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Artikelen 1–20