| Analysis of graphene nanoribbons as a channel material for field-effect transistors B Obradovic, R Kotlyar, F Heinz, P Matagne, T Rakshit, MD Giles, ... Applied Physics Letters 88 (14), 2006 | 460 | 2006 |
| Physics of hole transport in strained silicon MOSFET inversion layers EX Wang, P Matagne, L Shifren, B Obradovic, R Kotlyar, S Cea, M Stettler, ... IEEE Transactions on Electron Devices 53 (8), 1840-1851, 2006 | 174 | 2006 |
| Assessment of room-temperature phonon-limited mobility in gated silicon nanowires R Kotlyar, B Obradovic, P Matagne, M Stettler, MD Giles Applied Physics Letters 84 (25), 5270-5272, 2004 | 173 | 2004 |
| Novel forksheet device architecture as ultimate logic scaling device towards 2nm P Weckx, J Ryckaert, ED Litta, D Yakimets, P Matagne, P Schuddinck, ... 2019 IEEE International Electron Devices Meeting (IEDM), 36.5. 1-36.5. 4, 2019 | 90 | 2019 |
| Nanowire & nanosheet FETs for ultra-scaled, high-density logic and memory applications A Veloso, T Huynh-Bao, P Matagne, D Jang, G Eneman, N Horiguchi, ... Solid-State Electronics 168, 107736, 2020 | 80 | 2020 |
| Shell Charging and Spin Filling Sequences in Realistic Vertical Quantum Dots P Matagne, JP Leburton, DG Austing, S Tarucha Physical Models for Quantum Dots, 375-386, 2021 | 75 | 2021 |
| From the metal to the channel: A study of carrier injection through the metal/2D MoS 2 interface G Arutchelvan, CJL de la Rosa, P Matagne, S Sutar, I Radu, ... Nanoscale 9 (30), 10869-10879, 2017 | 73 | 2017 |
| Shell-Filling Effects and Coulomb Degeneracy in Planar Quantum Dot Structures S Nagaraja, P Matagne, VY Thean, JP Leburton, YH Kim, RM Martin Physical Models for Quantum Dots, 79-101, 2021 | 68 | 2021 |
| Understanding stress enhanced performance in Intel 90nm CMOS technology MD Giles, M Armstrong, C Auth, SM Cea, T Ghani, T Hoffmann, R Kotlyar, ... Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004., 118-119, 2004 | 66 | 2004 |
| Inversion mobility and gate leakage in high-k/metal gate MOSFETs R Kotlyar, MD Giles, P Matagne, B Obradovic, L Shifren, M Stettler, ... IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004 …, 2004 | 64 | 2004 |
| Modeling of via resistance for advanced technology nodes I Ciofi, PJ Roussel, Y Saad, V Moroz, CY Hu, R Baert, K Croes, A Contino, ... IEEE transactions on Electron Devices 64 (5), 2306-2313, 2017 | 61 | 2017 |
| Gate-all-around NWFETs vs. triple-gate FinFETs: Junctionless vs. extensionless and conventional junction devices with controlled EWF modulation for multi-VT CMOS A Veloso, G Hellings, MJ Cho, E Simoen, K Devriendt, V Paraschiv, ... 2015 Symposium on VLSI Technology (VLSI Technology), T138-T139, 2015 | 55 | 2015 |
| Vertical nanowire FET integration and device aspects A Veloso, E Altamirano-Sánchez, S Brus, BT Chan, M Cupak, M Dehan, ... ECS Transactions 72 (4), 31, 2016 | 54 | 2016 |
| Drive current enhancement in p-type metal–oxide–semiconductor field-effect transistors under shear uniaxial stress L Shifren, X Wang, P Matagne, B Obradovic, C Auth, S Cea, T Ghani, J He, ... Applied physics letters 85 (25), 6188-6190, 2004 | 48 | 2004 |
| Three-dimensional analysis of the electronic structure of cylindrical vertical quantum dots P Matagne, JP Leburton Physical Models for Quantum Dots, 387-417, 2021 | 45 | 2021 |
| Quantum mechanical calculation of hole mobility in silicon inversion layers under arbitrary stress E Wang, P Matagne, L Shifren, B Obradovic, R Kotlyar, S Cea, J He, Z Ma, ... IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004 …, 2004 | 44 | 2004 |
| Device-, circuit-& block-level evaluation of CFET in a 4 track library P Schuddinck, O Zografos, P Weckx, P Matagne, S Sarkar, Y Sherazi, ... 2019 Symposium on VLSI Technology, T204-T205, 2019 | 43 | 2019 |
| A physically-based analytic model for stress-induced hole mobility enhancement B Obradovic, P Matagne, L Shifren, E Wang, M Stettler, J He, MD Giles Journal of Computational Electronics 3, 161-164, 2004 | 43 | 2004 |
| Junctionless gate-all-around lateral and vertical nanowire FETs with simplified processing for advanced logic and analog/RF applications and scaled SRAM cells A Veloso, B Parvais, P Matagne, E Simoen, T Huynh-Bao, V Paraschiv, ... 2016 IEEE Symposium on VLSI Technology, 1-2, 2016 | 40 | 2016 |
| Front end stress modeling for advanced logic technologies SM Cea, M Armstrong, C Auth, T Ghani, MD Giles, T Hoffmann, R Kotlyar, ... IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004 …, 2004 | 40 | 2004 |
