| Dynamically controlled power reduction method and circuit for a graphics processor L Bajic, J Fry US Patent 8,102,398, 2012 | 65 | 2012 |
| Dynamic weight calculation in a digital power estimation and management system L Bajic, L Bajic US Patent 8,650,428, 2014 | 32 | 2014 |
| Apparatus and method for managing power among a plurality of processors sharing a thermal platform SD Presant, AJ Branover, O Khodorkovsky, L Bajic US Patent 9,348,656, 2016 | 30 | 2016 |
| AMD'S" LLANO" Fusion APU D Foley, M Steinman, A Branover, G Smaus, A Asaro, S Punyamurtula, ... 2011 IEEE Hot Chips 23 Symposium (HCS), 1-38, 2011 | 25 | 2011 |
| Compute substrate for Software 2.0 J Vasiljevic, L Bajic, D Capalija, S Sokorac, D Ignjatovic, L Bajic, ... IEEE micro 41 (2), 50-55, 2021 | 13 | 2021 |
| System and method for using virtual vector register files L Bajic, M Mantor, SZM Gilani, RM Koduri US Patent App. 15/191,339, 2017 | 12 | 2017 |
| Adaptive oscillator for clock generation JCW Wong, D Ignjatovic, M Rodionov, L Bajic, SV Kosonocky, ... US Patent 10,382,014, 2019 | 9 | 2019 |
| Processing core with metadata actuated conditional graph execution L Bajic, M Trajkovic, I Hamer, L Bajic, A Cejkov US Patent 11,113,051, 2021 | 7 | 2021 |
| Conditional graph execution based on prior simplified graph execution L Bajic, M Trajkovic, I Hamer US Patent App. 15/945,454, 2018 | 6 | 2018 |
| Processing core data compression and storage system L Bajic, A Cejkov, L Bajic US Patent 10,644,721, 2020 | 5 | 2020 |
| Processing core with metadata actuated conditional graph execution L Bajic, M Trajkovic, I Hamer US Patent 10,817,293, 2020 | 4 | 2020 |
| Processor cores using packet identifiers for routing and computation D Capalija, L Bajic, J Vasiljevic US Patent 11,269,628, 2022 | 3 | 2022 |
| Compute substrate for Software 2.0 L Bajic, J Vasiljevic 2020 IEEE Hot Chips 32 Symposium (HCS), 1-31, 2020 | 2 | 2020 |
| Processor bridge power management MB Steinman, AJ Branover, DJ Foley, L Bajic US Patent 9,043,625, 2015 | 2 | 2015 |
| Application data flow graph execution using network-on-chip overlay J Vasiljevic, D Capalija, Z Moudallal, U Aydonat, J Chu, SA Chin, L Bajic US Patent 11,934,897, 2024 | 1 | 2024 |
| Overlay layer hardware unit for network of processor cores I Matosevic, D Capalija, J Vasiljevic, U Aydonat, SA Chin, D Maksimovic, ... US Patent 11,734,224, 2023 | 1 | 2023 |
| Overlay layer for network of processor cores D Capalija, I Matosevic, J Vasiljevic, U Aydonat, A Lewycky, SA Chin, ... US Patent App. 17/945,045, 2023 | 1 | 2023 |
| Processing core with operation suppression based on contribution estimate L Bajic, M Trajkovic, I Hamer, S Gilani US Patent 10,585,679, 2020 | 1 | 2020 |
| Seamless place and route for heterogenous network of processor cores J Vasiljevic, L Bajic, D Capalija, S Sokorac US Patent 11,960,885, 2024 | | 2024 |
| Multiplication hardware block with adaptive fidelity control system L Bajic, M Trajkovic, S Gilani US Patent App. 17/955,539, 2024 | | 2024 |
